搜索 "asic" 找到 12 个结果
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Applicatio
Must-have verilog systemverilog modules
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in pl
RISC-V CPU Core (RV32IM)
Package manager and build abstraction tool for FPGA/ASIC development
SERV - The SErial RISC-V CPU
Haskell to VHDL/Verilog/SystemVerilog compiler
基于ESP32的简易合成器项目。
This stack contains hardware drivers, Gazebo plugins and other basic functionalities for the Neuronics Katana family of
ESP32与OLED配合麦克风实时解码莫尔斯电码显示。
开源项目结合AI智能垃圾箱与PCB拆解系统。