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⭐⭐⭐⭐☆ (4/5) 3172
fpga pynq verilog
basic_verilog

Must-have verilog systemverilog modules

⭐⭐⭐☆☆ (3/5) 1672
altera debounce delay
SpinalHDL

Scala based HDL

⭐⭐⭐☆☆ (3/5) 1504
fpga rtl scala
AXI片上通信高性能SystemVerilog模块

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

⭐⭐⭐☆☆ (3/5) 1412
asic axi axi4
DarkRISCV

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

⭐⭐⭐☆☆ (3/5) 1296
core fpga risc-v
SERV - 串行RISC-V CPU

SERV - The SErial RISC-V CPU

⭐⭐⭐☆☆ (3/5) 1004
asic fpga risc-v
clash-lang/clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

⭐⭐⭐☆☆ (3/5) 664
asic fpga hardware-description-language
tillitis/tillitis-key1

FPGA verilog and firmware for TKey, the flexible and open USB security key 🔑

⭐⭐⭐☆☆ (3/5) 132
fpga open-hardware open-source
TimRudy/ice-chips-verilog

IceChips is a library of all common discrete logic devices in Verilog

⭐⭐⭐☆☆ (3/5) 108
7400 digital-logic eda